Lightweight and Low-Latency AES Accelerator Using Shared SRAM

In this study, we propose a lightweight and low-latency advanced encryption standard (AES) accelerator. Instead of being connected to the bus through its own slave wrapper, proposed AES accelerator is located within wrapper static random-access memory (SRAM) directly attached SRAM. Hence, can access data in SRAM share space for storing expanded keys, resulting no time transferring input output data, resource usage power wastage repeated key expansion. The has latency 53 clock cycles per encryption/decryption process gate count 2912 when synthesized using 28 nm technology. similar that another with same 32-bit path; however, size 46.0% smaller. Furthermore, compared other accelerators 8-bit path, 3.0–22.0 times smaller slightly larger area.